`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/11/08 15:57:59
// Design Name: 
// Module Name: clk_div_module
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module clk_div_module#(
    parameter   CLK_DIV_NUM =   2
)(
    input       i_clk   ,
    input       i_rst   ,

    output      o_clk
    );


/*********parameter**********/

/*********wire***************/

/*********reg****************/
reg [15 : 0]    r_cnt   ;
reg             r_o_clk ;
/*********assign*************/
assign  o_clk = r_o_clk ;
/*********always*************/
always @(posedge i_clk,posedge i_rst ) begin
    if(i_rst)
        r_cnt   <=  16'd0;
    else if(r_cnt == (CLK_DIV_NUM >> 1)  - 1)
        r_cnt   <=  16'd0;
    else
        r_cnt   <=  r_cnt   +   16'd1;
end

always @(posedge i_clk,posedge i_rst ) begin
    if(i_rst)
        r_o_clk   <=  1'b0;
    else if(r_cnt == (CLK_DIV_NUM >> 1)  - 1)
        r_o_clk   <=  ~r_o_clk;
    else
        r_o_clk   <=  r_o_clk;
end

endmodule
